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ltm2882 1 2882fb typical a pplica t ion descrip t ion dual isolated rs232 module transceiver + power the ltm ? 2882 is a complete galvanically isolated dual rs232 module ? transceiver. no external components are required. a single 3.3v or 5v supply powers both sides of the interface through an integrated, isolated dc/dc converter. a logic supply pin allows easy interfacing with different logic levels from 1.62v to 5.5v, independent of the main supply. coupled inductors and an isolation power transformer provide 2500v rms of isolation between the line transceiver and the logic interface. this device is ideal for systems with different grounds, allowing for large common mode voltages. uninterrupted communication is guaranteed for common mode transients greater than 30kv/s. this part is compatible with the tia/eia-232-f standard. driver outputs are protected from overload and can be shorted to ground or up to 15v without damage. an auxiliary isolated digital channel is available. this channel allows confguration for half-duplex operation by control- ling the de pin. enhanced esd protection allows this part to withstand up to 10kv (human body model) on the transceiver interface pins to isolated supplies and across the isolation barrier to logic supplies without latchup or damage. isolated dual rs232 module transceiver fea t ures a pplica t ions n ul rated dual rs232 transceiver: 2500v rms ul recognized ? file #e15178 n isolated dc power: 5v at up to 200ma n no external components required n 1.62v to 5.5v logic supply for flexible digital interfacing n high speed operation 1mbps for 250pf/3k load 250kbps for 1nf/3k load 100kbps for 2.5nf/3k tia/eia-232-f load n 3.3v (ltm2882-3) or 5v (ltm2882-5) operation n no damage or latchup to 10kv hbm esd on isolated rs232 interface or across isolation barrier n high common mode transient immunity: 30kv/s n common mode working voltage: 560v peak n true rs232 compliant output levels n low profle (15mm 11.25mm) surface mount bga and lga packages n isolated rs232 interface n industrial communication n test and measurement equipment n breaking rs232 ground loops 1mbps operation 2882 ta01a on din t1in r1out t2in r2out dout t1out r1in t2out r2in ltm2882 3.3v (ltm2882-3) 5v (ltm2882-5) v l v cc gnd gnd2 isolation barrier onoff v cc2 de 5v available current: 150ma (ltm2882-5) 100ma (ltm2882-3) 400ns/div driver outputs tied to receiver inputs tout load = 250pf + rin rout load = 150pf 10v/div 5v/div tin t1out/r1in t2out/r2in 5v/div 2882 ta01b r1out r2out l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltm2882 2 2882fb p in c on f igura t ion a bsolu t e maxi m u m r a t ings v cc to gnd .................................................. C 0.3v to 6v v l to gnd .................................................... C0 .3v to 6v v cc2 to gnd2 ............................................... C 0.3v to 6v logic inputs t1in, t2in, on, din to gnd ........ C 0.3v to (v l + 0.3v) de to gnd2 ............................. C0.3v to (v cc2 + 0.3v) logic outputs r1out, r2out to gnd ............... C 0.3v to (v l + 0.3v) dout to gnd2 ........................ C0 .3v to (v cc2 + 0.3v) driver output voltage t1out, t2out to gnd2 ........................... C 15v to 15v receiver input voltage r1in, r2in to gnd2 ............................... C25 v to 25v operating temperature range (note 4) ltm2882c ......................................... 0 c t a 70c ltm2882i ..................................... C 40c t a 85c ltm2882h ................................... C4 0c t a 105c maximum internal operating temperature ............ 1 25c storage temperature range .................. C 55c to 125c peak refow temperature (soldering, 10 sec) ....... 24 5c (note 1) v cc gnd gnd2 a b c d e f g h i j k l 1 2 3 4 5 6 7 8 lga package 32-pin (15mm 11.25mm 2.8mm) t jmax = 125c, ja = 29c/w, jctop = 27.9c/w, jcbottom = 18c/w, jb = 22.7c/w, weight = 1.1g bga package 32-pin (15mm 11.25mm 3.42mm) t jmax = 125c, ja = 30c/w, jctop = 27.8c/w, jcbottom = 19.3c/w, jb = 24c/w, weight = 1.1g top view v cc2 v l ondint1in r1out t2in de dout t1out r1in t2out r2in r2out lead free finish tray part marking* package description temperature range ltm2882cy-3#pbf ltm2882cy-3#pbf ltm2882y-3 32-pin (15mm 11.25mm 3.42mm) bga 0c to 70c ltm2882iy-3#pbf ltm2882iy-3#pbf ltm2882y-3 32-pin (15mm 11.25mm 3.42mm) bga C40c to 85c ltm2882hy-3#pbf ltm2882hy-3#pbf ltm2882y-3 32-pin (15mm 11.25mm 3.42mm) bga C40c to 105c ltm2882cy-5#pbf ltm2882cy-5#pbf ltm2882y-5 32-pin (15mm 11.25mm 3.42mm) bga 0c to 70c ltm2882iy-5#pbf ltm2882iy-5#pbf ltm2882y-5 32-pin (15mm 11.25mm 3.42mm) bga C40c to 85c ltm2882hy-5#pbf ltm2882hy-5#pbf ltm2882y-5 32-pin (15mm 11.25mm 3.42mm) bga C40c to 105c ltm2882cv-3#pbf ltm2882cv-3#pbf ltm2882v-3 32-pin (15mm 11.25mm 2.8mm) lga 0c to 70c ltm2882iv-3#pbf ltm2882iv-3#pbf ltm2882v-3 32-pin (15mm 11.25mm 2.8mm) lga C40c to 85c ltm2882cv-5#pbf ltm2882cv-5#pbf ltm2882v-5 32-pin (15mm 11.25mm 2.8mm) lga 0c to 70c ltm2882iv-5#pbf ltm2882iv-5#pbf ltm2882v-5 32-pin (15mm 11.25mm 2.8mm) lga C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ or d er in f or m a t ion
ltm2882 3 2882fb e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. ltm2882-3 v cc = 3.3v, ltm2882-5 v cc = 5.0v, v l = v cc , and gnd = gnd2 = 0v, on = v l unless otherwise noted. symbol parameter conditions min typ max units supplies v cc input supply range ltm2882-3 l 3.0 3.3 3.6 v ltm2882-5 l 4.5 5.0 5.5 v v l logic supply range l 1.62 5.5 v i cc input supply current on = 0v l 0 10 a ltm2882-3, no load l 24 30 ma ltm2882-5, no load l 17 21 ma v cc2 regulated output voltage, loaded ltm2882-3 de = 0v, i load = 100ma l 4.7 5.0 v ltm2882-3, h-grade, i load = 90ma l 4.75 v ltm2882-5 de = 0v, i load = 150ma l 4.7 5.0 v v cc2(noload) regulated output voltage, no load de = 0, no load 4.8 5.0 5.35 v effciency i cc2 = 100ma, ltm2882-5 (note 2) 65 % i cc2 output supply short-circuit current l 250 ma driver v old driver output voltage low r l = 3k l C5 C5.7 v v ohd driver output voltage high r l = 3k l 5 6.2 v i osd driver short-circuit current v t1out , v t2out = 0v, v cc2 = 5.5v l 35 70 ma i ozd driver three-state (high impedance) output current de = 0v, v t1out , v t2out = 15v l 0.1 10 a receiver v ir receiver input threshold input low l 0.8 1.3 v input high input high, h-grade l l 1.7 2.5 2.7 v v v hysr receiver input hysteresis l 0.1 0.4 1.0 v r in receiver input resistance C15v (v r1in , v r2in ) 15v l 3 5 7 k logic v ith logic input threshold voltage on, t1in, t2in, din = 1.62v v l < 2.35v l 0.25?v l 0.75?v l v on, t1in, t2in, din = 2.35v v l 5.5v l 0.4 0.67?v l v de l 0.4 0.67?v cc2 v i inl logic input current l 1 a v hys logic input hysteresis t1in, t2in, din (note 2) 150 mv v oh logic output high voltage r1out, r2out i load = C1ma (sourcing), 1.62v v l < 3.0v i load = C4ma (sourcing), 3.0v v l 5.5v l l v l C 0.4 v l C 0.4 v v dout, i load = C4ma (sourcing) l v cc2 C 0.4 v v ol logic output low voltage r1out, r2out i load = 1ma (sinking), 1.62v v l < 3.0v i load = 4ma (sinking), 3.0v v l 5.5v l l 0.4 0.4 v v dout, i load = 4ma (sinking) l 0.4 v esd (hbm) (note 2) rs232 driver and receiver protection (t1out, t2out, r1in, r2in) to (v cc2 , gnd2) 10 kv (t1out, t2out, r1in, r2in) to (v cc , v l , gnd) 10 kv isolation boundary (v cc2 , gnd2) to (v cc , v l , gnd) 10 kv
ltm2882 4 2882fb swi t ching c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. ltm2882-3 v cc = 3.3v, ltm2882-5 v cc = 5.0v, v l = v cc , and gnd = gnd2 = 0v, on = v l unless otherwise noted. symbol parameter conditions min typ max units maximum data rate (t1in to t1out, t2in to t2out) r l = 3k, c l = 2.5nf (note 3) l 100 kbps r l = 3k, c l = 1nf (note 3) l 250 kbps r l = 3k, c l = 250pf (note 3) l 1000 kbps maximum data rate (din to dout) c l = 15pf (note 3) l 10 mbps driver driver slew rate (6v/ t thl or t tlh ) r l = 3k, c l = 50pf (figure 1) l 150 v/s t phld , t plhd driver propagation delay r l = 3k, c l = 50pf (figure 1) l 0.2 0.5 s t skewd driver skew |t phld C t plhd | r l = 3k, c l = 50pf (figure 1) 40 ns t pzhd , t pzld driver output enable time de = , r l = 3k, c l = 50pf (figure 2) l 0.6 2 s t phzd , t plzd driver output disable time de = , r l = 3k, c l = 50pf (figure 2) l 0.3 2 s receiver t phlr , t plhr receiver propagation delay c l = 150pf (figure 3) l 0.2 0.4 s t skewr receiver skew |t phlr C t plhr | c l = 150pf (figure 3) 40 ns t rr , t fr receiver rise or fall time c l = 150pf (figure 3) l 60 200 ns auxiliary channel t phll , t plhl propagation delay c l = 15pf, t r and t f < 4ns (figure 4) l 60 100 ns t rl , t fl rise or fall time c l = 150pf (figure 4) l 60 200 ns power supply power-up time on = to v cc2(min) l 0.2 2 ms isola t ion c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. ltm2882-3 v cc = 3.3v, ltm2882-5 v cc = 5.0v, v l = v cc , and gnd = gnd2 = 0v, on = v l unless otherwise noted. symbol parameter conditions min typ max units v iso rated dielectric insulation voltage 1 minute, derived from 1 second test 2500 v rms 1 second (note 5) 4400 v common mode transient immunity v l = on = 3.3v, v cm = 1kv, ?t = 33ns (note 2) 30 kv/s v iorm maximum working insulation voltage (notes 2, 5) 560 400 v peak v rms partial discharge v pr = 1050 v peak (notes 2, 5) 5 pc input to output resistance (notes 2, 5) 10 9 input to output capacitance (notes 2, 5) 6 pf creepage distance (notes 2, 5) 9.48 mm note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by design and not subject to production test. note 3: maximum data rate is guaranteed by other measured parameters and is not tested directly. note 4: this device includes over-temperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above specifed maximum operating junction temperature may result in device degradation or failure. note 5: tests performed from gnd to gnd2, all pins shorted each side of isolation barrier.
ltm2882 5 2882fb typical p er f or m ance c harac t eris t ics v cc supply current vs load capacitance (dual transceiver) v cc supply current vs data rate (dual transceiver) driver short-circuit current vs temperature receiver input threshold vs temperature v cc supply current vs temperature v cc supply current vs temperature t a = 25c, ltm2882-3 v cc = 3.3v, ltm2882-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. temperature (c) ?50 v cc current (ma) 30 25 15 20 10 50 0 100 2882 g01 125 25 ?25 75 no load v cc = 3.3v ltm2882-3 v cc = 5.0v ltm2882-5 temperature (c) ?50 v cc current (ma) 70 60 40 35 45 55 65 50 30 50 0 100 2882 g02 125 25 ?25 75 t1out and t2out baud = 100kbps r l = 3k, c l = 2.5nf v cc = 3.3v ltm2882-3 v cc = 5.0v ltm2882-5 load capacitance (nf) 0 v cc current (ma) 100 250kbps, ltm2882-3 100kbps, ltm2882-3 19.2kbps, ltm2882-3 19.2kbps, ltm2882-5 250kbps, ltm2882-5 100kbps, ltm2882-5 80 40 50 30 70 90 60 20 1 2 2882 g03 2.5 0.5 1.5 data rate (kbps) 0 v cc current (ma) 140 100 40 80 120 60 20 400 800 2882 g04 1000 200 600 5.0v c l = 1nf 5.0v c l = 250pf 3.3v c l = 1nf 3.3v c l = 250pf temperature (c) ?50 threshold voltage (v) 3.0 2.0 0.5 1.5 2.5 1.0 0 50 0 100 2882 g05 125 input low 25 ?25 75 input high load capacitance (nf) 0 slew rate (v/s) 70 50 10 20 40 60 30 0 4 2 2882 g06 5 3 1 falling rising temperature (c) ?50 short-circuit current (ma) 50 40 25 20 15 35 45 30 10 0 50 75 100 2882 g07 125 ?25 25 sourcing sinking driver slew rate vs load capacitance receiver output voltage vs load current load current(ma) 0 output voltage (v) 6 1 2 4 5 3 0 8 4 2882 g09 10 6 2 v l = 5.5v v l = 3.3v v l = 1.62v driver disabled leakage current vs temperature at 15v temperature (c) ?50 leakage current (na) 1000 10 0.01 1 100 0.1 0.001 0 50 75 100 2882 g08 125 ?25 25 v tout = 15v
ltm2882 6 2882fb typical p er f or m ance c harac t eris t ics driver outputs exiting shutdown driver outputs enable/disable logic input threshold vs v l supply voltage t a = 25c, ltm2882-3 v cc = 3.3v, ltm2882-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. v l supply voltage (v) 0 threshold voltage (v) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 0 4 5 2 2882 g10 6 3 1 input high input low 100s/div 5v/div t1out t1out on t2out t2out 2882 g12 de = v cc2 de = dout, d in = v l 2s/div 5v/div 2v/div t1out t2out 2882 g13 de operating through 35kv/s common mode transients 50ns/div 500v/div 2v/div t1in r1out * * multiple sweeps of common mode transients 2v/div 2882 g14 t1out = r1in v cc2 output voltage vs load current load current (ma) 0 v cc2 voltage (v) 5.2 5.0 4.6 4.7 4.9 5.1 4.8 4.5 150 50 250 2882 g11 300 3.0v 100 200 v cc = 3.0v to 3.6v, ltm2882-3 v cc = 4.5v to 5.5v, ltm2882-5 5.5v 5.0v 4.5v 3.6v 3.3v
ltm2882 7 2882fb v cc2 load step response 100s/div 50ma/div 200mv/div 2882 g18 v cc2 ripple and noise v cc2 power effciency 10s/div 100mv/div 2882 g17 t1in = 250kbps t1out, t2out, r l = 3k load current (ma) 0 efficiency (%) power loss (w) 70 60 20 30 50 40 10 1.2 1.0 0.2 0.4 0.8 0.6 0 200 250 100 2882 g16 300 150 50 ltm2882-3 ltm2882-5 t a = 25c typical p er f or m ance c harac t eris t ics t a = 25c, ltm2882-3 v cc = 3.3v, ltm2882-5 v cc = 5v, v l = 3.3v, and gnd = gnd2 = 0v, on = v l unless otherwise noted. v cc2 surplus current vs temperature temperature (c) ?50 v cc2 current (ma) 300 200 50 150 250 100 0 50 0 100 2882 g15 125 25 ?25 75 t1out and t2out baud = 100kbps r l = 3k, c l = 2.5nf v cc2 = 4.8v v cc = 3.3v ltm2882-3 v cc = 5.0v ltm2882-5
ltm2882 8 2882fb t es t c ircui t s figure 3. receiver timing measurement figure 4. auxiliary channel timing measurement 2882 f03 rin rout c l t phlr t plhr t fr t rr 10% ?v l 90% 90% 10% 1.5v 3v v ol v oh ?3v rin rout t r , t f 40ns 2882 f04 din dout c l t plhl t phll t rl t fl 90% 10% 10% 90% ?v l ?v cc2 v l v oh v ol 0v din dout figure 1. driver slew rate and timing measurement figure 2. driver enable/disable times 2882 f01 r l tin tout c l t plhd t phld t thl t tlh 3v 0v ?3v ?v l v l v old v ohd 0v tin tout t r , t f 40ns 2882 f02 r l de tout t r , t f 40ns 0 or v l c l t pzhd t pzld t phzd t plzd v old ? 0.5v v ohd ? 0.5v ?v cc2 v cc2 v ohd v old 0v 0v 0v tout tout de ?5v 5v
ltm2882 9 2882fb logic side r2out (pin a1): channel 2 rs232 inverting receiver output. controlled through isolation barrier from receiver input r2in. under the condition of an isolation communi- cation failure r2out is in a high impedance state. t2in (pin a2): channel 2 rs232 inverting driver input. a logic low on this input generates a high on isolated output t2out. a logic high on this input generates a low on isolated output t2out. do not foat. r1out (pin a3): channel 1 rs232 inverting receiver output. controlled through isolation barrier from receiver input r1in. under the condition of an isolation communi- cation failure r1out is in a high impedance state. t1in (pin a4): channel 1 rs232 inverting driver input. a logic low on this input generates a high on isolated output t1out. a logic high on this input generates a low on isolated output t1out. do not foat. din (pin a5): general purpose non-inverting logic input. a logic high on din generates a logic high on isolated output dout. a logic low on din generates a logic low on isolated output dout. do not foat. on (pin a6): enable. enables power and data communica- tion through the isolation barrier. if on is high the part is enabled and power and communications are functional to the isolated side. if on is low the logic side is held in reset and the isolated side is unpowered. do not foat. v l (pin a7): logic supply. interface supply voltage for pins din, r2out, t2in, r1out, t1in, and on. operat - ing voltage is 1.62v to 5.5v. internally bypassed to gnd with 2.2f. v cc (pins a8, b7-b8): supply voltage. operating volt- age is 3.0v to 3.6v for ltm2882-3, and 4.5v to 5.5v for ltm2882-5. internally bypassed to gnd with 2.2f. gnd (pins b1-b6): circuit ground. isolated side gnd2 (pins k1-k7): isolated side circuit ground. these pads should be connected to the isolated ground and/or cable shield. v cc2 (pins k8, l7-l8): isolated supply voltage output. internally generated from v cc by an isolated dc/dc con- verter and regulated to 5v. supply voltage for pins r1in, r2in, de, and dout. internally bypassed to gnd2 with 2.2f. r2in (pin l1): channel 2 rs232 inverting receiver input. a low on isolated input r2in generates a logic high on r2out. a high on isolated input r2in generates a logic low on r2out. impedance is nominally 5k in receive mode or unpowered. t2out (pin l2): channel 2 rs232 inverting driver output. controlled through isolation barrier from driver input t2in. high impedance when the driver is disabled (de pin is low). r1in (pin l3): channel 1 rs232 inverting receiver input. a low on isolated input r1in generates a logic high on r1out. a high on isolated input r1in generates a logic low on r1out. impedance is nominally 5k in receive mode or unpowered. t1out (pin l4): channel 1 rs232 inverting driver output. controlled through isolation barrier from driver input t1in. high impedance when the driver is disabled (de pin is low). dout (pin l5): general purpose non-inverting logic output. logic output connected through isolation barrier to din. de (pin l6): driver output enable. a low input forces both rs232 driver outputs, t1out and t2out, into a high impedance state. a high input enables both rs232 driver outputs. do not foat. p in func t ions
ltm2882 10 2882fb b lock diagra m 2882 bd 2.2f 2.2f v cc v cc2 gnd2 de dout t1out r1in t2out r2in v l 2.2f gnd on din t1in t2in r2out r1out dc/dc converter isolated communi- cations interface isolated communi- cations interface 5v reg v dd v ee v dd v dd v ee v ee 5k 5k
ltm2882 11 2882fb figure 5. v cc and v l are independent 2882 f05 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 any voltage from 1.62v to 5.5v 3.0v to 3.6v ltm2882-3 4.5v to 5.5v ltm2882-5 external device v l v cc v cc2 gnd isolation barrier gnd2 applica t ions in f or m a t ion overview the ltm2882 module transceiver provides a galvani - cally-isolated robust rs232 interface, powered by an integrated, regulated dc/dc converter, complete with decoupling capacitors. the ltm2882 is ideal for use in networks where grounds can take on different voltages. isolation in the ltm2882 blocks high voltage differences, eliminates ground loops and is extremely tolerant of com- mon mode transients between grounds. error-free opera - tion is maintained through common mode events greater than 30kv/s providing excellent noise isolation. module technology the ltm2882 utilizes isolator module technology to translate signals and power across an isolation barrier. signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using coreless transformers formed in the module substrate. this system, complete with data refresh, error checking, safe shutdown on fail, and extremely high common mode immunity, provides a robust solution for bidirectional signal isolation. the module technology provides the means to combine the isolated signaling with our advanced dual rs232 transceiver and powerful isolated dc/dc converter in one small package. dc/dc converter the ltm2882 contains a fully integrated isolated dc/dc converter, including the transformer, so that no external components are necessary. the logic side contains a full- bridge driver, running at about 2mhz, and is ac-coupled to a single transformer primary. a series dc blocking capacitor prevents transformer saturation due to driver duty cycle imbalance. the transformer scales the primary voltage, and is rectifed by a full-wave voltage doubler. this topology eliminates transformer saturation caused by secondary imbalances. the dc/dc converter is connected to a low dropout regulator (ldo) to provide a regulated low noise 5v output, v cc2 . an integrated boost converter generates a 7v v dd supply and a charge pumped C6.3v v ee supply. v dd and v ee power the output stage of the rs232 drivers and are regulated to levels that guarantee greater than 5v output swing. the internal power solution is suffcient to support the transceiver interface at its maximum specifed load and data rate, and has the capacity to provide additional 5v power on the isolated side v cc2 and gnd2 pins. v cc and v cc2 are each bypassed internally with 2.2f ceramic capacitors. v l logic supply a separate logic supply pin v l allows the ltm2882 to inter - face with any logic signal from 1.62v to 5.5v as shown in figure 5. simply connect the desired logic supply to v l . there is no interdependency between v cc and v l ; they may simultaneously operate at any voltage within their specifed operating ranges and sequence in any order. v l is bypassed internally by a 2.2f capacitor. hot plugging safely caution must be exercised in applications where power is plugged into the ltm2882s power supplies, v cc or v l , due to the integrated ceramic decoupling capacitors. the parasitic cable inductance along with the high q char - acteristics of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage ratings and damage the ltm2882. refer to linear technology ap - plication note 88, entitled ceramic input capacitors can cause overvoltage transients for a detailed discussion and mitigation of this phenomenon.
ltm2882 12 2882fb channel timing uncertainty multiple channels are supported across the isolation bound- ary by encoding and decoding of the inputs and outputs. the technique used assigns t1in/r1in the highest priority such that there is no jitter on the associated output chan- nels t1out/r1out, only delay. this preemptive scheme will produce a certain amount of uncertainty on t2in/r2in to t2out/r2out and din to dout. the resulting pulse width uncertainty on these low priority channels is typically 6ns, but may vary up to about 40ns. half-duplex operation the de pin serves as a low-latency driver enable for half- duplex operation. the de pin can be easily driven from the logic side by using the uncommitted auxiliary digital channel, din to dout. each driver is enabled and disabled in less than 2s, while each receiver remains continuously active. this mode of operation is illustrated in figure 6. applica t ions in f or m a t ion figure 6. half-duplex confguration using d out to drive de 2882 f06 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 3.3v (ltm2882-3) 5v (ltm2882-5) v l v cc v cc2 gnd gnd2 isolation barrier t x r x driver overvoltage and overcurrent protection the driver outputs are protected from short-circuits to any voltage within the absolute maximum range of 15v relative to gnd2. the maximum current is limited to no more than 70ma to maintain a safe power dissipation and prevent damaging the ltm2882. receiver overvoltage and open circuit the receiver inputs are protected from common mode voltages of 25v relative to gnd2. each receiver input has a nominal input impedance of 5k relative to gnd2. an open circuit condition will generate a logic high on each receivers respective output pin. rf, magnetic field immunity the ltm2882 has been independently evaluated and has successfully passed the rf and magnetic feld immunity testing requirements per european standard en 55024, in accordance with the following test standards: en 61000-4-3 radiated, radio-frequency, electromagnetic field immunity en 61000-4-8 power frequency magnetic field immunity en 61000-4-9 pulsed magnetic field immunity tests were per formed using an unshielded test card de- signed per the data sheet pcb layout recommendations. specifc limits per test are detailed in table 1. table 1 test frequency field strength en 61000-4-3, annex d 80mhz to 1ghz 10v/m 1.4mhz to 2ghz 3v/m 2ghz to 2.7ghz 1v/m en 61000-4-8, level 4 50hz and 60hz 30a/m en 61000-4-8, level 5 60hz 100a/m* en 61000-4-9, level 5 pulse 1000a/m *non iec method
ltm2882 13 2882fb a pplica t ions i n f or m a t ion pcb layout the high integration of the ltm2882 makes pcb layout very simple. however, to optimize its electrical isolation characteristics, emi, and thermal performance, some layout considerations are necessary. ? under heavily loaded conditions v cc and gnd current can exceed 300ma.suffcient copper must be used on the pcb to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level. similarly, the v cc2 and gnd2 conductors must be sized to support any external load current. these heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity. ? input and out put dec oupling is not req uired, sin ce the se components are integrated within the package. an ad- ditional bulk capacitor with a value of 6.8f to 22f is recommended. the high esr of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. for emi sensitive applications, an additional low esl ceramic capacitor of 1f to 4.7f, placed as close to the power and ground terminals as possible, is recommended. alternatively, a number of smaller value parallel capacitors may be used to reduce esl and achieve the same net capacitance. ? do not place copper on the pcb between the inner col- umns of pads. this area must remain open to withstand the rated isolation voltage. ? the use of solid ground planes for gnd and gnd2 is recommended for non-emi critical applications to optimize signal fdelity, thermal performance, and to minimize rf emissions due to uncoupled pcb trace conduction. the drawback of using ground planes, where emi is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between gnd and gnd2. if ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate rf emissions. ? for large ground planes a small capacitance ( 330pf) from gnd to gnd2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. discrete capacitance will not be as effective due to parasitic esl. in addition, volt- age rating, leakage, and clearance must be considered for component selection. embedding the capacitance within the pcb substrate provides a near ideal capacitor and eliminates component selection issues; however, the pcb must be 4 layers. care must be exercised in applying either technique to insure the voltage rating of the barrier is not compromised. the pcb layout in figures 7a to 7e show the low emi demo board for the ltm2882. the demo board uses a combination of emi mitigation techniques, including both embedded pcb bridge capacitance and discrete gnd to gnd2 capacitors. two safety rated type y2 capacitors are used in series, manufactured by murata, part number ga342qr7gf471kw01l. the embedded capacitor ef- fectively suppresses emissions above 400mhz, whereas the discrete capacitors are more effective below 400mhz. emi performance is shown in figure 8, measured using a gigahertz transverse electromagnetic (gtem) cell and method detailed in iec 61000-4-20, testing and mea - surement techniques C emission and immunity testing in transverse electromagnetic waveguides.
ltm2882 14 2882fb applica t ions in f or m a t ion technology figure 7a. low emi demo board layout figure 7b. low emi demo board layout (dc1747a), top layer figure 7c. low emi demo board layout (dc1747a), inner layer 1
ltm2882 15 2882fb a pplica t ions i n f or m a t ion figure 7d. low emi demo board layout (dc1747a), inner layer 2 figure 7e. low emi demo board layout (dc1747a), bottom layer frequency (mhz) 0 dbv/m 60 50 40 30 20 ?20 ?10 0 ?30 400 200 600 2882 f08 1000 300 100 500 700 900800 10 detector = quasipeak r bw = 120khz v bw = 300khz sweep time = 17sec dc1747a-a dc1747a-b cispr 22 class 8 limit figure 8. low emi demo board emissions
ltm2882 16 2882fb t ypical applica t ions figure 9. single line dual half-duplex isolated transceiver 2882 f09 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 3.3v (ltm2882-3) 5v (ltm2882-5) v l v cc gnd gnd2 3.3k isolation barrier t x r x 3.3k figure 13. isolated multirail power supply with switched outputs figure 10. driving larger capacitive loads figure 11. 1.8v microprocessor interface 2882 f10 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 3.3v (ltm2882-3) 5v (ltm2882-5) v l v cc gnd gnd2 isolation barrier 3k c l data rate (kbps) 100 5 250 2 1000 0.5 c l (nf) 2882 f11 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 p v l v cc gnd 1.8v 3.3v (ltm2882-3) 5v (ltm2882-5) isolation barrier gnd2 figure 12. isolated 5v power supply 2882 f12 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 v l v cc v cc2 gnd 3.3v (ltm2882-3) 5v (ltm2882-5) 5v regulated 150ma (ltm2882-5) 100ma (ltm2882-3) isolation barrier gnd2 onoff 2882 f13 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 3.3v (ltm2882-3) 5v (ltm2882-5) 5v regulated 7v switched return ?6.3v switched v l v cc v cc2 gnd gnd2 isolation barrier onoff
ltm2882 17 2882fb p ackage descrip t ion bga package 32-lead (15mm 11.25mm 3.42mm) (reference ltc dwg # 05-08-1851 rev b) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view 4 pin ?a1? corner x y aaa z aaa z package bottom view 3 see notes suggested pcb layout top view bga 32 0110 rev b ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? detail a pin 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 detail a ?b (32 places) f g h l j k e a b c d 2 1 4 3 5678 detail b substrate 0.27 ? 0.37 2.45 ? 2.55 // bbb z d a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee 0.630 0.025 ? 32x symbol a a1 a2 b b1 d e e f g aaa bbb ccc ddd eee min 3.22 0.50 2.72 0.73 0.60 nom 3.42 0.60 2.82 0.78 0.63 15.0 11.25 1.27 12.70 8.89 max 3.62 0.70 2.92 0.83 0.66 0.15 0.10 0.20 0.30 0.15 notes dimensions total number of balls: 32 e b e e b a2 f g
ltm2882 18 2882fb p ackage descrip t ion lga package 32-lead (15mm 11.25mm 2.82mm) (reference ltc dwg # 05-08-1773 rev ?) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222 5. primary datum -z- is seating plane 6. the total number of pads: 32 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature detail b detail b substrate mold cap 0.290 ? 0.350 2.400 ? 2.600 bbb z z package top view 11.25 bsc 15.00 bsc 4 pad ?a1? corner x y aaa z aaa z package bottom view 3 pads see notes suggested pcb layout top view lga 32 0308 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? 8.89 bsc 1.27 bsc pad 1 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 symbol aaa bbb eee tolerance 0.10 0.10 0.05 detail a 0.630 0.025 ? 32x s yxeee detail c 0.630 0.025 ? 32x s yxeee f g h l j k e a b c d 2 1 4 3 567 2.69 ? 2.95 detail a 12.70 bsc 8 detail c
ltm2882 19 2882fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 3/10 changes to features add bga package to pin confguration, order information and package description sections changes to lga package in pin confguration section update to pin functions update to rf, magnetic field immunity section pcb layout isolation considerations section replaced 1 2, 15 2 9 12 13 b 3/11 h-grade parts added. refected throughout the data sheet. 1-20
ltm2882 20 2882fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0311 rev b ? printed in usa r ela t e d p ar t s typical a pplica t ions part number description comments ltm2881 isolated rs485/rs422 module transceiver with low emi integrated dc/dc converter 20mbps, 15kv hbm esd, 2500v rms isolation with 1w power ltm2883 spi/digital module isolator with adjustable 12.5v and 5v regulated power up to 10mhz, 10kv hbm esd, 2500v rms isolator ltc2870/ltc2871 rs232/rs485 multiprotocol transceivers with integrated termination 20mbps rs485 and 500kbps rs232, 26kv esd, 3v to 5v operation ltc2804 1mbps rs232 transceiver dual channel, full-duplex, 10kv hbm esd ltc1535 isolated rs485 transceiver 2500 v rms isolation with external transformer driver figure 16. isolated gate drive with overcurrent detection figure 14. isolated rs232 interface with handshaking figure 15. isolated dual inverting level translator 2882 f14 on din t1in r2out t2in r2out de dout t1out r1in t2out r2in ltm2882 c peripheral v l v cc r x t x rts cts t x d r x d p y p z v cc2 gnd gnd2 3.3v (ltm2882-3) 5v (ltm2882-5) isolation barrier 2882 f15 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 v l v cc gnd 3.3v (ltm2882-3) 5v (ltm2882-5) gnd2 1.62v to 5.5v isolation barrier onoff v l 0v v l 0v ?25v to 0v 3v to 25v ?25v to 0v 3v to 25v 2882 f16 on din t1in r1out t2in r2out de dout t1out r1in t2out r2in ltm2882 v l v cc v cc2 gnd gnd2 +v s 3k irlml2402 irlml6402 470pf 1k 1k 3.3v (ltm2882-3) 5v (ltm2882-5) isolation barrier reset fault pwma pwmb r ilim = 0.6/max current 47pf cmpt2369-ltv 3k logic level fets

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